Optimising Neuromorphic Hardware Architectures for Efficiency and Security

Apply and key information  

This project is funded by:

    • Department for the Economy (DfE)

Summary

Sustainability in electronics is often approached through re-use and recycling, but the idea of repairing hardware to extend its lifetime has received much less attention.

Biological systems are naturally robust and able to adapt to damage, and these ideas are increasingly being used to inspire new forms of Artificial Intelligence (AI) and hardware design.

At Ulster University, our research team has already developed bio-inspired methods for distributed repair, fault-tolerant interconnects, and secure hardware.

These approaches allow electronic systems to adapt to failures, handle security breaches and keep operating for longer, improving both energy efficiency and sustainability.

To achieve this in real hardware for resource constrained secure IoT systems, and wearable health edge AI devices, we need better ways to design neuromorphic or brain-inspired computing systems.

These mechanisms must be energy-efficient, reconfigurable, and secure, especially for edge devices.

This PhD project focuses on designing Energy-Efficient and Secure Neuromorphic Computing Systems by proposing novel low-power and secure circuits/systems design techniques for constrained secure IoT edge devices.

The aim is to explore how these techniques can support energy-efficient learning mechanisms while also maintaining strong security.

A key outcome will be an FPGA prototype demonstrating a small neural network with secure, configurable weight storage.

The project will help advance neuromorphic computing by enabling hardware that is more robust, repairable, scalable, and energy-efficient.

You will join the CNET research team at Ulster University, working with experts in neuromorphic hardware, FPGA design and hardware security.

You will have access to modern Intel/AMD FPGAs, laboratory equipment, and existing bio-inspired hardware designs and datasets.

This research supports global goals for sustainable and secure electronics and builds on strong collaborations through initiatives such as SPEAR and NERVOUS - offering excellent opportunities for training and professional development.

Through this work, the PhD candidate will contribute to next-generation neuromorphic computing.

Skills required of the applicant:

A background in computer engineering/electronics engineering, or a related field will be advantageous, along with knowledge of the following:

*low-power circuits/system design for ASIC,
*Verilog based FPGA based system design,
*hardware security

Essential criteria

Applicants should hold, or expect to obtain, a First or Upper Second Class Honours Degree in a subject relevant to the proposed area of study.

We may also consider applications from those who hold equivalent qualifications, for example, a Lower Second Class Honours Degree plus a Master’s Degree with Distinction.

In exceptional circumstances, the University may consider a portfolio of evidence from applicants who have appropriate professional experience which is equivalent to the learning outcomes of an Honours degree in lieu of academic qualifications.

  • Experience using research methods or other approaches relevant to the subject domain
  • A demonstrable interest in the research area associated with the studentship

Desirable Criteria

If the University receives a large number of applicants for the project, the following desirable criteria may be applied to shortlist applicants for interview.

  • First Class Honours (1st) Degree
  • Masters at 70%
  • For VCRS Awards, Masters at 75%
  • Experience using research methods or other approaches relevant to the subject domain
  • Work experience relevant to the proposed project
  • Publications - peer-reviewed
  • Experience of presentation of research findings
  • Use of personal initiative as evidenced by record of work above that normally expected at career stage.

Equal Opportunities

The University is an equal opportunities employer and welcomes applicants from all sections of the community, particularly from those with disabilities.

Appointment will be made on merit.

Funding and eligibility

This project is funded by:

  • Department for the Economy (DfE)

This scholarship will cover tuition fees and provide a maintenance allowance of £21,000* (tbc) per annum for three years (subject to satisfactory academic performance).  A Research Training Support Grant (RTSG) of approximately £900 per annum is also available.

To be eligible for these scholarships, applicants must meet the following criteria:

  • Be a UK National, or
  • Have settled status, or
  • Have pre-settled status, or
  • Have indefinite leave to remain or enter, or
  • be an Irish National

Applicants should also meet the residency criteria which requires that they have lived in the EEA, Switzerland, the UK or Gibraltar for at least the three years preceding the start date of the research degree programme.

Applicants who already hold a doctoral degree or who have been registered on a programme of research leading to the award of a doctoral degree on a full-time basis for more than one year (or part-time equivalent) are NOT eligible to apply for an award.

Due consideration should be given to financing your studies.

*Part time PhD scholarships may be available, based on 0.5 of the full time rate, and will require a six year registration period

Recommended reading

[1] Javed A, Harkin J, McDaid L, Liu J (2021), "Spiking Neural Network-based Structural Health Monitoring Hardware System," IEEE Symposium Series on Computational Intelligence, pp. 1-7.

[2]. Liu et al. (2019) Exploring Self-Repair in a Coupled Spiking Astrocyte Neural Network. IEEE Transactions on Neural Networks and Learning Systems, 30(3), 865–875.

[3]. Johnson A. et al. (2018) Fault-Tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs. International Conference on VLSI Design and Embedded Systems (VLSID), 49-54.

[4] Shvan Karim et al. (2020) AstroByte: Multi-FPGA Architecture for Accelerated Simulations of Spiking Astrocyte Neural Networks, Design, Automation and Test in Europe (DATE).

[5] Li R, Gong Y, Huang H, et al. (2024) Photonics for Neuromorphic Computing: Fundamentals, Devices, and Opportunities. Advanced Materials. doi: 10.1002/adma.202312825.

[6] K. Lee et al., “Secure Machine Learning Hardware: Challenges and Progress [Feature],” in IEEE Circuits and Systems Magazine, vol. 25, no. 1, pp. 8-34, Firstquarter 2025.

The Doctoral College at Ulster University

Key dates

Submission deadline
Friday 27 February 2026
04:00PM

Interview Date
tbc

Preferred student start date
14th September 2026

Applying

Apply Online  

Contact supervisor

Professor Jim Harkin

Other supervisors