Networks-on-Chip (NoC) Interconnect Strategy for Scalable AI Hardware

Apply and key information  

This project is funded by:

    • SEUPB Peace Plus (SPEAR)

Summary

The Semiconductor and Photonics Education and Research (SPEAR) Centre, funded by PEACEPLUS and managed by the Special EU Programmes Body (SEUPB), is a cross-border initiative connecting Ulster University and ATU with an all-island network of research groups and industry partners. Supported by Tyndall National Institute and advised by Seagate Technology, SPEAR focuses on advancing photonics research, training, and innovation in response to the EU Chips Act 2023, while addressing regional skills and infrastructure gaps.

A core component of SPEAR is a doctoral training programme involving 15 PhD students, delivered in collaboration with ATU, Tyndall National Institute, and Seagate Technology. Three students will be based at Ulster University (Derry~Londonderry campus) and will join a joint Doctoral College with researchers at ATU (Letterkenny campus) and Tyndall. The programme includes co-supervision, shared training, summer schools, industry engagement, and access to advanced facilities. This PhD studentship is now open for applications.


PhD Topic: Networks-on-Chip (NoC) Interconnect Strategy for Scalable Neuromorphic Hardware

Next generation AI hardware, referred to as Neuromorphic hardware, mimics the brain using spiking neural networks, enabling efficient, parallel, and event-driven computation. Its low power and real-time processing make it well suited for edge applications such as IoT, smart manufacturing, and energy-efficient data centres. A key challenge is designing scalable interconnects between neurons, synapses, and glial cells. Networks-on-Chip (NoCs) provide a scalable communication framework for such systems, supporting event-based data transfer.

Recent work at Ulster has developed astrocyte-neuron networks that integrate glial cells to enable adaptability and self-repair. However, scaling these systems introduces significant interconnect challenges. Advances in photonics offer high-speed, energy-efficient on-chip communication, creating opportunities to combine NoC and photonic approaches for next-generation neuromorphic hardware.

This PhD aims to innovate in a new NoC interconnect solution for large-scale neuromorphic hardware, which utilise photonics-based mechanisms. The PhD work will examine impacts on NoC design, including routers and topologies. The PhD project has access to modern Intel (Altera)\AMD (Xilinx) FPGAs and a large suite of Agilent logic analyser/oscilloscope instrumentation; existing in-house reference FPGA-based neuromorphic NoC designs are available to support initial explorations.

Essential criteria

Applicants should hold, or expect to obtain, a First or Upper Second Class Honours Degree in a subject relevant to the proposed area of study.

We may also consider applications from those who hold equivalent qualifications, for example, a Lower Second Class Honours Degree plus a Master’s Degree with Distinction.

In exceptional circumstances, the University may consider a portfolio of evidence from applicants who have appropriate professional experience which is equivalent to the learning outcomes of an Honours degree in lieu of academic qualifications.

  • Experience using research methods or other approaches relevant to the subject domain
  • A demonstrable interest in the research area associated with the studentship

Desirable Criteria

If the University receives a large number of applicants for the project, the following desirable criteria may be applied to shortlist applicants for interview.

  • First Class Honours (1st) Degree
  • Masters at 70%
  • Experience using research methods or other approaches relevant to the subject domain
  • Work experience relevant to the proposed project
  • Publications - peer-reviewed
  • Experience of presentation of research findings
  • Use of personal initiative as evidenced by record of work above that normally expected at career stage.

Equal Opportunities

The University is an equal opportunities employer and welcomes applicants from all sections of the community, particularly from those with disabilities.

Appointment will be made on merit.

Funding and eligibility

This project is funded by:

  • SEUPB Peace Plus (SPEAR)

The scholarship will cover tuition fees at the Home rate and a maintenance allowance of £20,516 per annum for three years (subject to satisfactory academic performance).

  • Candidates with pre-settled or settled status under the EU Settlement Scheme, who also satisfy a three year residency requirement in the UK prior to the start of the course for which a Studentship is held MAY receive a Studentship covering fees and maintenance.
  • Republic of Ireland (ROI) nationals are eligible to receive a Studentship covering fees and maintenance (ROI nationals don’t need to have pre-settled or settled status under the EU Settlement Scheme to qualify).
  • Other non-ROI EU applicants are ‘International’ are not eligible for this source of funding.
  • Applicants who already hold a doctoral degree or who have been registered on a programme of research leading to the award of a doctoral degree on a full-time basis for more than one year (or part-time equivalent) are NOT eligible to apply for an award.

Recommended reading

S. Biglari, F. Hosseini, A. Upadhyay and H. Zhao, "Survey of Network-on-Chip (NoC) for Heterogeneous Multicore Systems," 2024 IEEE 17th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Kuala Lumpur, Malaysia, 2024, pp. 155-162

Bahareh Asadi, Syed Maqsood Zia Ahmad, et al. “Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A Survey”, Journal of Electronic Testing 39(1), February 2023.

The Doctoral College at Ulster University

Key dates

Submission deadline
Monday 27 July 2026
04:00PM

Interview Date
10 August 2026

Preferred student start date
14 September 2026

Applying

Apply Online  

Contact supervisor

Professor Jim Harkin

Other supervisors